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About Us Our expertise

3D PLUS is the world's foremost provider of high-density 3D electronic products, specializing in cutting-edge stacking technology for bare chips and components. Our solutions are designed to meet the critical demands for high reliability, superior performance, and compact size in modern electronics.

Innovative 3D Technology

Our innovative 3D technology involves the vertical stacking of electronic devices along the Z-axis. This process begins with the horizontal placement of electronic devices on a layer, where they are internally connected. These layers are then stacked vertically using advanced vertical interconnection techniques, optimizing space and enhancing functionality.

Leading-Edge Stacking Technologies

3D PLUS offers a comprehensive portfolio of patented stacking technologies, ranging from standard packages to die-size and wafer-level stacking processes. While each process may vary, they all adhere to four core principles:

  • n-High Stacking: This involves the stacking of heterogeneous, non-modified standard die, wafers, packages, and passive components.
  • High Yield: Achieved through rigorous testing and screening of each layer before stacking.
  • Reliability: Ensured by our advanced Bus Metal-Edge interconnection techniques, which utilize a cold process.
  • Proven Technologies: We employ simple, well-established technologies to guarantee reliability and efficiency.

(*) n-High means a stack of n levels.

Benefits of Our Technology

Our technologies reduce the size and weight of components by a factor of at least 10 compared to existing solutions. With the capability to stack up to 10 semiconductor devices within 1 mm, our 3D PLUS Ultra Low Profile Modules are unparalleled in the industry.

Versatile Applications

Our technology responds to a wide range of applications, from low-volume, space-qualified projects to high-volume industrial uses. 3D PLUS is uniquely qualified for space applications by major space agencies, including ESA, NASA, and JPL, making it the only technology of its kind in the world.

TECHNOLOGY LINEUP

3D PLUS provides four different very flexible Stack Technology Flows

Standard packages stack

With the capability to stack n-High any standard packages from the industry, this process flow is based on very simple and well-proven technologies. A large products portfolio using this technology relies on TSOPs packages. This capability domain is also qualified by European Space Agency (ESA) for Space applications.

 

Flex Process-Die Stack

With the capability to stack n-High any non-modified standard die (even with different sizes and technology), this process flow enables to embed the best semiconductors together in one single highly miniaturized package. High reliability and resistance to harsh environments, and very good manufacturing yield are also key benefits of this die stacking technology.

Flex Process- SIP Stack

This process has the unique capability to stack n-High any heterogeneous active, passive and opto-electroniques devices in a single highly miniaturized package. This is the most efficient technology for the building complex System-in-Packages (SiPs). This capability domain is also qualified by European Space Agency (ESA) for Space Application.

 

Wafer Level Stack WDOD™

Based on the use of standard wafers (die without “TSV”), and with the capability to stack die with different sizes up to 10 levels, our wafer level stack technology named WDoD™ (Wirefree Die-on-Die) achieves smaller forms factors and Ultra Low Profile 3D stack.

Depending on the product’s performance requirements and targeted market, the relevant stacking process will be selected within 3D PLUS technology portfolio in order to bring the best added value and benefits for our customers designs.

KEY FEATURES AND BENEFITS

KEY FEATURES BENEFITS
The components are stacked up Small form factor, size reduction on the PCB, weight savings
Use of Heterogeneous components (bare dice, packaged components chips, passive passive components with different sizes and technologies Best combination of any standard semiconductor devices and technologies that cannot be realized monolithic SoC approaches
Use of Standard wafers (die without “TSV”) Die sourcing flexibility
Easy access to the industry
Cost effectiveness
WDoD™ is the only really available Wafer level stacking process
The die and components mounted on flex can be tested and screened before stacking Stacking of n levels with excellent yield
The standard packaged component have been tested before stacking Stacking of n levels with excellent yield
The components are fixed into resin High mechanical resistance, resistance to harsh environments
Humidity resistance enhancement
Used for Space applications
The interconnection is reduced and simplified Higher electrical performance and signal integrity
Simplified PWB layout
Electrical performance are significantly improved, since parasitic effects (resistance, inductance and capacity) are reduced in the same proportions as the reduction in volume.
The components can be shielded Considerable parasitic effect decrease
Use of well proven technologies Very High reliability
ESA Qualified Capability Domain and Manufacturing line (PID 3300-0546) Stack can be used in any ESA and other European spacecraft and Space segment hardware in accordance with the Requirements for the Process Capability Approval for manufacturing Lines of Non-Hermetic Microelectronic modules ESCC256601
Simplified Manufacturing processes Flexibility and short development time of new designs Cost effectiveness
Stack are connection independent Compatibiliy with all types of components insertion processes: SMT (Gull wing & BGA), Gluing (Conductive column T&B), Through Hole (PGA),…