Controller IP Core
RIMC DDR2 and RIMC DDR3 are SDRAM Radiation Intelligent Memory Controller IP cores designed to work respectively with 3D PLUS DDR2 or DDR3 memory modules to achieve a radiation hardened DDR2/DDR3 solution.
Those IP Cores, besides being a DDR controller mitigates SEU and protect against SEFI.
RIMC DDR can be configured to support different types of ECC such as Hamming and Reed Solomon , and the user can configure the data bus width.
The RIMC DDR IP Core is defined by different interfaces: the user interface, which is AMBA compliant, and the DDR PHY interface, compliant to DFI 2.1, to send commands and data to the DDR memory components through the DDR PHY (depends on different FPGAs).
The user interface (depending on the version DDR2 or DDR3 IP) may contain AHB bus, APB and/or UPI interface bus for user dynamic configuration.
The RIMC controller can be configured by the core logic using different AMBA interfaces:
- Slave AHB/AXI interface with specific address mapping
- Slave APB interface dedicated to internal registers
High Performance DDR3 controller
- DDR PHY interface DFI 2.1 compliant
- High speed (up to 800 Mhz for DDR3) memory controller
- User interface AMBA compliant (AXI/AHB/APB)
- TID Flip bit protection
- SEU mitigation
- SEFI Protection
- Scrubbing for SEU and SERE corrections
- RIMC DDR2 = Variable user data width: from x8 to x64b
- RIMC DDR3 = Variable user data width: from x8 to 128b
- Selectable hamming or Reed-Solomon coding schemes
- Configurable number of DDR ranks to increase memory capacity
- Clock & ODT settings compatible with 3D PLUS modules
- Capability to manage redundant memory designs
- Supports burst of 4 and burst of 8 DDR interfaces
- DDR memory scrubbing can be enabled or disabled
- Scrubbing can be performed at a user-defined frequency
- Selectable DRAM refresh time
- Bank management algorithm is instantiated inside the RIMC
- Configurable through AMBA interfaces
- Dynamically configurable via the APB slave interface
- User can implement an AHB and/or AXI slave interface, 1 to 8 ports can be instantiated
- Provides a direct access to DDR memory array with a controller bypass mode
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