Controller IP Core


3DIPMC700-1 is a fully configurable DDR2 SDRAM radiation intelligent memory controller IP core designed to work with 3D PLUS DDR2 memory modules to achieve a radiation hardened DDR2 solution. The 3DIPMC700-1 can be configured to support different types of ECC for data width applications from 8b up to 64b; providing SEU mitigation and SEFI protection.

The RIMC IP Core is defined by 2 interfaces: the user interface, which is AMBA compliant, and the DDR PHY interface,  compliant to DFI 2.1,  to send commands and data to the DDR memory components through the DDR PHY (depends on different FPGAs). The user interface contains at least one AHB bus, and may contain an optional APB bus for user dynamic configuration. The RIMC controller can be configured by the core logic using 2 different AMBA interfaces:
-Slave AHB/AXI interface with specific address mapping
-Slave APB interface dedicated to internal registers

Key Features

Variable user data width: from x8 to x64b

Selectable Hamming or Reed-Solomon coding schemes

Configurable number of DDR2 ranks to increase memory capacity

Clock & ODT settings compatible with 3D PLUS modules

Capability to manage redundant memory designs

Supports burst of 4 and burst of 8 DDR2 interfaces

DDR memory scrubbing can be enabled or disabled

Scrubbing can be performed at a user-defined frequency

Selectable DRAM refresh time

Bank management algorithm is instantiated inside the RIMC

User interface AMBA compliant (AXI/AHB/APB)

Configurable through AMBA interfaces

Configurable number of AHB slave interfaces

DDR PHY interface DFI 2.1 compliant

Dynamically configurable via the APB slave interface.

User can implement an AHB and/or AXI slave interface, 1 to 8 ports can be instantiated

Provides a direct access to DDR memory array with a controller bypass mode



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