Wafer Level Stack - WDoD™

Overview

Based on the use of standard wafers (die without « TSV »), our patented wafer level stack technology named WDoD™ (Wirefree Die-on-Die) has the unique capability to stack n-High any kind of die (technology process, size and thickness).

This technology allows gaining a factor of 25 to 100 on weight and volume comparing to the other existing 3D Modules.

Thanks to the test and burn-in capability for each layer prior to stacking (Known Good Rebuilt Wafer concept) and stacks parallel manufacturing process, the WDoD™ technology is the most efficient technology for building complex System-In-Packages (SiPs). It enables achieving a combination that cannot be realized with monolithic System-on-Chip (SoC) approaches, and it has a lower development and manufacturing cost, and a faster time to market.

The WDoD™ technology is developed in the frame of internal R&D since 2002. The WDoD™ technology was also core for several associated European projects such as the Eureka/Pidea Program "WALPACK" (20M€, 2002 to 2005) for which 3D Plus received the “LXNX” Award from EUREKA in 2006 in Roma, and the Eureka/Pidea Program "e-CUBES" (12M€, 2006 to 2009).
Height specific patents have been filed for the WDoD™ process. The WDoD™ process flow is referenced as FLOW 3.

FLOW 3 Process Flow Chart

The steps 1 to 6 show the « Known Good Rebuilt Wafer» (2D Process):

The steps 13 to 21 show the stacking of the « Known Good Rebuilt Wafers » (3D Process).

For steps 7 to 12, two options can be used:

  • OPTION 1: Only one layer has to be burned-in
  • OPTION 2 : Several layers have to be burned-in before stacking, so a subsystem is built with two levels or more and burned-in before stacking with the other layers as in the Package on Package approach (PoP).

Key Features Benefits
The components are stacked up Decrease of the volume/weight by 25 to 100 times with regard to the existing 3D modules
Ultra small form factor and Low profile Size of the 3D module after stacking is equal to the size of the larger die plus 100µm around it
Stacking of any kind of die (size and thickness) Best combination of any standard semiconductor devices and technologies that cannot be realized with monolithic SoC approaches
More than 1 die per level
Use of standard wafers (die without « TSV ») Die sourcing flexibility
Easy access to the industry
Cost effectiveness
WDoD™ is the only really available Wafer level stacking process
Test and burn-in (if necessary) of each level before stacking thanks to the Rebuilt Wafer Concept Stacking of n levels with excellent yield
Parallel processing thanks to the Rebuilt Wafer Concept Cost effectiveness
Use of well proven technologies Very High reliability
High Resistance to harsh environment (thermal, vibrations, …)

FLOW 3 Products Overview

  • Known Good Rebuilt wafers (100 µm thickness) using standard wafers
    (die without « TSV »)
  • 8 Layers (0.8mm) Memory Stack built with WDoD™ process flow