Flex Process - SiP Stack

Overview

This patented process has the unique capability to stack n-High any heterogeneous active, passive, Opto-electronics and MEMS/MOEMS devices in a single highly miniaturized package and with almost no limit for the merging of heterogeneous technologies (standard non modified Die or packages with different sizes).

This 3D technology is based on the stacking of electronic components (chips, plastic packages, sensors) placed on a film layer generally 35mm wide, and so called flex. This solutions allows testing and screening the components of each layer before stacking. This is the key feature for building ‘n’-High stacks with a very good yield. The flex are then stacked vertically and connected together thanks to a vertical interconnection technique.

This technology allows gaining a factor of at least 10 on weight and volume of the components comparing to existing solutions. This is the most efficient technology for building complex System-In-Packages (SiPs). It enables achieving a combination that cannot be realized with monolithic System-on-Chip (SoC) approaches, and it has a lower development cost and a faster time to market. This capability domain is referenced as FLOW 2 and is qualified by European Space Agency (ESA) for Space applications.

FLOW 2 SiP Process Flow Chart

Key Features Benefits
The components are stacked up Small form factor, Size reduction on the PCB, weight savings
Use of Heterogeneous components (bare dice, packaged components, passive chips) with different sizes and technologies Best combination of any standard semiconductor devices and technologies that cannot be realized with monolithic SoC approaches
The die and components mounted on flex can be tested and screened before stacking Stacking of n levels with excellent yield
The standard packaged components have been tested before stacking Stacking of n levels with excellent yield
The components are fixed into resin High mechanical resistance, resistance to harsh environments
Humidity resistance enhancement
Used for Space applications
The interconnection is reduced and simplified Higher electrical performance and signal integrity
Simplified PWB layout
Electrical performances are significantly improved, since parasitic effects (resistance, inductance and capacity) are reduced in the same proportions as the reduction in volume.
The components can be shielded Considerable parasitic effect decrease
Use of well proven technologies Very High reliability
ESA Qualified Capability Domain and manufacturing line (PID 3300-0546) Stacks can be used intended for use in any ESA and other European spacecraft and Space segment hardware in accordance with the procurement requirements defined in the ECSS-Q-60-05A
Simplified Manufacturing processes Flexibility and short development time of new designs
Cost effectiveness
Stacks are connection independent Compatibility with all types of components insertion processes: SMT (Gull wing & BGA), Gluing (Conductive column T&B), Through Hole (PGA),…

FLOW 2 SiP Products Overview

  • 4 Layers Computer SiP – Crossection view with µProcessor, ASIC, ROM, RAM and all passive chips
  • 4 Layers Computer SiP with 2 FPGA, ROM and RAM and all passive chips
     
  • 11 Layers Computer SiP with DSP, ASICs, ROM, RAM and all passive chips
     
  • T/R Module SiP with embedded connectors for Phase Array Radar
     
  • Shielded Low Noise Amplifier SiP with octagonal shape
  • Image Sensor & Processing Module for Guidance Electronics
  • 3 Layers Power Converter SiP