3D PLUS is a world leading supplier of advanced high density 3D microelectronic products and bare die and wafer level stacking technology meeting the demand for high reliability, high performance and very small size electronics.
Its 3D technology concept and innovation consists of interconnecting electronic devices which have been stacked along the Z dimension. As in the following illustration, the electronic devices are first placed horizontally alongside one another on a Layer and internally connected. The Layers are then stacked vertically and connected thanks to a vertical interconnection technique.
3D PLUS portfolio of patented and leading edge stacking technologies starts with standard packages scale upward to die-size and wafer level stacking processes.
Although the detailed process flows can be different, our stacking technology all rely on the same four Key principles:
- n-High(*) Stacking of heterogeneous non modified standard die, wafer, packages and passive components
- Excellent yield thanks to the test/screening of each layer before stacking
- High reliability Bus Metal - Edge interconnection techniques (cold process)
- Use of very simple and well proven technologies
(*) n-High means a stack of n levels.
They allow gaining a factor of at least 10 on size and weight of the components comparing to existing solutions, and with a capability of stacking up to 10 semiconductor devices within 1mm, 3D PLUS Ultra Low Profile Modules are unique.
Our technology offer responds to a diverse range of needs and requirements going from low volume-space qualified up to high volume-industrial applications. It is the only one in the world that is qualified for Space applications by the major Space Agencies ESA, NASA and JPL.
3D PLUS provides four different very flexible Stack Technology Flows
Standard Packages Stack
With the capability to stack n-High any standard packages from the industry, this process flow is based on very simple and well proven technologies. A large products portfolio using this technology relies on TSOPs packages. This capability domain is also qualified by European Space Agency (ESA) for Space application.
Flex Process – Die Stack
With the capability to stack n-High any non modified standard die (even with different sizes and technology), this process flow enables to embed the best semiconductors together in one single highly miniaturized package. High reliability and resistance to harsh environments, and very good manufacturing yield are also key benefits of this die stacking technology.
Flex Process – SiP Stack
This process has the unique capability to stack n-High any heterogeneous active, passive and Opto-electronics devices in a single highly miniaturized package. This is the most efficient technology for building complex System-In-Packages (SiPs). This capability domain is also qualified by European Space Agency (ESA) for Space application.
Wafer Level Stack - WDoD™
Based on the use of standard wafers (die without « TSV »), and with the capability to stack die with different sizes up to 10 levels, our wafer level stack technology named WDoD™ (Wirefree Die-on-Die) achieves smaller form factors and Ultra Low Profile 3D stacks.
Depending on the product’s performance requirements and targeted market, the relevant stacking process will be selected within 3D PLUS technology portfolio in order to bring the best added value and benefits for our customer designs.
Key Features and Benefits
|The components are stacked up||Small form factor, Size reduction on the PCB, weight savings|
|Use of Heterogeneous components (bare dice, packaged components, passive chips) with different sizes and technologies||Best combination of any standard semiconductor devices and technologies that cannot be realized with monolithic SoC approaches|
|Use of standard wafers (die without « TSV »)||Die sourcing flexibility
Easy access to the industry
WDoD™ is the only really available Wafer level stacking process
|The die and components mounted on flex can be tested and screened before stacking||Stacking of n levels with excellent yield|
|The standard packaged components have been tested before stacking||Stacking of n levels with excellent yield|
|The components are fixed into resin||High mechanical resistance, resistance to harsh environments
Humidity resistance enhancement
Used for Space applications
|The interconnection is reduced and simplified||Higher electrical performance and signal integrity
Simplified PWB layout
Electrical performances are significantly improved, since parasitic effects (resistance, inductance and capacity) are reduced in the same proportions as the reduction in volume.
|The components can be shielded||Considerable parasitic effect decrease|
|Use of well proven technologies||Very High reliability|
|ESA Qualified Capability Domain and manufacturing line (PID 3300-0546)||Stacks can be used intended for use in any ESA and other European spacecraft and Space segment hardware in accordance with the procurement requirements defined in the ECSS-Q-60-05A|
|Simplified Manufacturing processes||Flexibility and short development time of new designs
|Stacks are connection independent||Compatibility with all types of components insertion processes: SMT (Gull wing & BGA), Gluing (Conductive column T&B), Through Hole (PGA),…|
Inventor of 3D stacked Electronics for Space
High Quality referential with ISO and Space Agencies Certifications
Our support teams are everywhere you are to ensure your satisfaction
Rugged components able to withstand harsh environments and space radiation effects
Dense, fast, rad hardened, System in Packages, miniaturized
Over 16 years of flight heritage and 100 000 modules in Space